There has been the ever present problem of providing an architecture permitting multiple host processors to efficiently communicate with multiple numbers of peripherals using different protocols. The difficulties are compounded when the host processors operate at different clock frequencies from the connecting I/O subsystems and peripherals and also use different message passing protocols.
The present multiple computer system network bridges the gap of handling normally incompatible digital modules via an architecture which permits efficient interoperability such that a host processor protocol using a single word and a first clock rate can functionally communicate with a modular input/output subsystem using a four word message protocol and a second clock rate with the added capability of communication with a variety of different peripheral units through specialized channel interface adaptors.
The interbus interface module operates within an Input/Output Subsystem (IOM) which relieves the Central Processing Modules (CPM) of I/O functions thus freeing the CPMs to work on higher priority tasks while the IOM provides rapid throughput for data communication and control to various types of peripheral units.